1. Field of the Invention
The present invention relates to a data access circuit for a Central Processing Unit (CPU).
2. Background of the Related Art
FIG. 1 illustrates a related art data access circuit for a Central Processing Unit (CPU). The related art data access circuit for a CPU includes a program counter 110 for constantly increasing addresses for a command extraction, a memory 120 for outputting a data corresponding to the output address from the program counter 110, a command decoder 130 for decoding the output data from the memory 120 and a command execution unit 140 for executing the decoded command from the command decoder 130.
When a program is executed, the program counter 110 increases addresses for command extraction from a predetermined address level by counting a clock signalCLK and outputs the increased addresses to the memory 120. When the memory 120 outputs the data corresponding to a region designated by an output address from the program counter 110, the command decoder 130 decodes the data to a command. The command execution unit 140 executes the commands decoded by the command decoder 130, and at the same time the program counter 110 increases the previous addresses by counting the clock signal CLK. The program counter 110 increases the previous address by a predetermined amount. Then, the program counter 110 outputs the increased address to the memory 120. When the memory 120 again outputs the data corresponding to the output address of the program counter 110, the commands are executed through the command decoder 130 and the command execution unit 140 in the above-described operation.
The related art CPU can be classified into a CISC structure and an RISC structure. Corresponding pipe line structures for CISC and RISC as shown in FIGS. 2 and 3 are configured to perform a fetch step F for reading a command, a decoding step D for interpreting the read command, an execution step E for executing the interpreted command, and a write back step WB for storing the executed result.
In the CISC structure CPU, since the command structure is configured by various lengths, not with a fixed length, it is possible to express complicated commands as one command. However, as shown in FIG. 2, a one word command is read at one clock period, and a two word command is read in two clock periods. Thus, a multi-word command is read in a few clock periods to execute a corresponding command.
As shown in FIG. 3, since the RISC structure CPU is configured to process commands each having the same length, it is possible to read the commands at one clock period. Since each command is read at one clock period, the command processing is very simply performed. Thus, a high speed processing is enabled as compared to the CISC structure.
However, the related art data access circuits have various disadvantages. In the related art data access circuits, it is possible to execute a complicated program by using one command because the commands of the CISC structure CPU have various lengths. However, when reading the CISC commands having shorter lengths and the commands having longer lengths, the command extraction time is different. In this case, the command reading and processing operations are complicated, the system performance is degraded, and a command processing speed is reduced.
The RISC structure CPU is configured to process commands having a predetermined length. Further, the RISC structure CPU reads commands at one time. Thus, the RISC structure CPU overcomes the disadvantages of the CPU of the CISC structure. However, since the lengths of the commands are identical and there is a predetermined limit for configuring the command processing system, it is impossible to execute the complicated commands by using one command. Thus, the code conversion efficiency of the RISC structure CPU is degraded.
A conventional decoder for the semiconductor memory device will now be described. FIG. 4 is a block diagram showing a conventional decoder system for a semiconductor memory device. Generally, a semiconductor memory device uses memory elements and a decoder for selecting memory words, together with memory cells, designated by input addresses. The conventional semiconductor memory device includes xe2x80x9cmxnxe2x80x9d binary memory cells 2 for accommodating xe2x80x9cmxe2x80x9d words of xe2x80x9cnxe2x80x9d bits, and an address decoder 1 for selecting each word. Each binary memory cell is a basic design block of the semiconductor memory device.
Two address inputs are connected to the address decoder 1, which is operated by a memory enable signal. If the memory enable signal sent to the address decoder 1 is xe2x80x9c0xe2x80x9d, the output of the address decoder 1 becomes xe2x80x9c0xe2x80x9d so that no word can be selected. If a memory enable signal sent to the address decoder 1 is xe2x80x9c1xe2x80x9d, one of four words is selected according to the value of the two address inputs. Thus, in the conventional semiconductor device, if the address decoder 1 receives an address, memory cells of many bytes on the designated row are simultaneously accessed. In this case, if a reading/writing signal is xe2x80x9c1xe2x80x9d, storage values of a binary memory cell 2 on designated words pass through three OR gates and are produced through output ports. Since other binary memory cells 2 generate xe2x80x9c0xe2x80x9d, they don""t affect the output. If the reading/writing signal is xe2x80x9c0xe2x80x9d, information standby at an input port is stored in a binary memory cell 2 on a designated word.
As described above, the conventional semiconductor memory device has various disadvantages and problems. The conventional semiconductor device only provides accessibility to the memory cells on a designated row upon receiving an address in an address decoder. It cannot provide continuity in input of addresses. Therefore, if when storing data with lengths and addresses over two rows, since the semiconductor memory device operates in divided steps for each of the rows, the operation speed is very low.
An object of the present invention to provide a semiconductor device data access circuit and method that overcomes at least the problems and disadvantages of the related art.
Another object of the present invention is to provide an address alignment system that can access many bytes of continued memory cells for any selected address.
Another object of the present invention is to provide an address alignment system that can access many variable length instruction/data for an input address.
Another object of the present invention is to provide an address alignment system that can access many variable length instruction/data for an input address in a single clock period.
Another object of the present invention to provide a data access circuit and method for a CPU that processes various length commands at high speed and one at a time.
Another object of the present invention is to provide a data access circuit and method that extracts commands irrespective of the corresponding lengths at one time by increasing a program count value as much as the length of the currently extracted command before designating the address of the next command.
To achieve the at least above objects in whole or in part, there is provided a data access circuit for a CPU according to the present invention that includes a program counter that increases a previous address by a length of a currently decoded command to compute the next address. A data storing unit outputs a data of a region corresponding to an output address from the program counter, and a data alignment unit judges the output address from the program counter to sequentially align data output from the data storing unit. A command decoding unit interprets the data from the data alignment unit to output a length value from the interpreted data to the program counter and a decoded command. A command execution unit executes the decoded command from the command decoding unit.
To further achieve the objects in whole or in part, there is provided a data access circuit for a CPU according to the present invention that includes a program counter that computes an output address based on a current command length, a data storage device that outputs data corresponding to the output address from the program counter, a data alignment device that aligns the output data from the data storage device and a decoding device that decodes a current command and a current command length among the aligned data from the data alignment device.
To further achieve the objects in whole or in part, there is provided a data access circuit for a CPU according to the present invention that includes a program counter that modifies a current memory address according to a currently decoded command length and computes a next memory address, a memory array that outputs a prescribed amount of data responsive to the next memory address from the program counter, wherein the prescribed amount of data is not less than a maximum CPU command length, wherein the memory array uses two or more address decoders and two or more memory cell arrays to output the prescribed amount of data at one time, a data alignment device that receives the prescribed amount of data from the memory array and aligns the prescribed amount of data according to the next memory address received from the program counter, a command decoder that decodes a subset of the aligned prescribed amount of data to output a variable length command and its variable command length, wherein the variable command length is transmitted to the program counter as the currently decoded command length, and a command execution device that receives and executes the variable length command from the command decoder.
To further achieve the objects in whole or in part, there is provided a data access circuit for a CPU according to the present invention that includes computing an output address based on a previous command length, outputting a prescribed amount of data from a plurality of data storage devices corresponding to the output address, wherein the prescribed amount of data is not less than a maximum command length, aligning the prescribed amount of data from the data storing device according to the output address, decoding a current command length and a current command in order starting from a front portion among the aligned prescribed amount of data, wherein the current command length is variable, and executing the current variable length command decoded from the aligned data, wherein the output address is recomputed based on the current command length.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.